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19-4535; Rev 2; 2/10
Low-Power, High-Performance NTSC/PAL Video Decoder
General Description
The MAX9526 is a low-power video decoder that converts NTSC or PAL composite video signals to 8-bit or 10-bit YCbCr component video compliant with the ITUR BT.656 standard. The device powers up in fully operational mode and automatically configures itself to decode the detected input standard. The MAX9526 typically consumes 200mW of power in normal operation and typically less than 100W in shutdown mode. An internal 10-bit, 54MHz analog-to-digital converter (ADC) samples the input with four times oversampling. The MAX9526 features a DC restoration circuit with offset correction and automatic gain control to accurately optimize the full-scale range of the ADC. An integrated analog anti-aliasing filter eliminates the need for external filtering. The MAX9526 includes a 2:1 input multiplexer with automatic signal selection based on activity at the inputs. An internal line-locked phase-locked loop (PLL) generates the sample clock and the line-locked clock (LLC) output to provide an ITU-compliant output. Alternatively, the PLL can be configured to provide a sample clock and output clock at 2x and 1x the frequency of the crystal oscillator, respectively. The MAX9526 provides a multiline adaptive comb filter to reduce cross-chrominance and cross-luminance artifacts. A single 1.8V supply is used for both the digital and analog supplies. The digital outputs operate from a separate +1.7V to +3.45V supply to allow direct connection to a wide range of digital processors. The MAX9526 operates over the -40C to +125C automotive temperature range and is available in both a 28-pin QSOP and a 32-pin TQFN (5mm x 6mm).
PART MAX9526AEI+ MAX9526AEI/V+ MAX9526ATJ+
Features
o Supports All NTSC and PAL Standards NTSC M, NTSC J, NTSC 4.43, PAL B/G/H/I/D, PAL M, PAL N, PAL 60 o Easy to Configure and Operate with Only 16 User-Programmable Registers o Automatic Configuration and Standard Select o 10-Bit 4x Oversampling (54Msps) ADC with True 10-Bit Digital Processing o Flexible Output Formatting 10-Bit Parallel ITU-R BT.656 Output with Embedded TRS 8-Bit Parallel ITU-R BT.656 Output with Separate HS and VS o +1.8V Digital and Analog Supply Voltage o +1.7V to +3.45V Digital I/O Supply Voltage o Full Automotive Temperature Range (-40C to +125C) o Low-Power Modes Shutdown (< 100W typ) Sleep Mode with Continuous Activity Detection (< 5mW typ) o 2-to-1 Video Input Mux with AGC
MAX9526
Ordering Information
TEMP RANGE -40C to +125C -40C to +125C -40C to +125C PIN-PACKAGE 28 QSOP 28 QSOP 32 TQFN-EP*
MAX9526ATJ/V+ -40C to +125C 32 TQFN-EP* +Denotes lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. *EP = Exposed pad.
Applications
Automotive Entertainment Systems Collision Avoidance Systems Security Surveillance/CCTV Systems Televisions
XTAL/OSC SYNC PROCESSING, CLOCK GENERATION, AND PLL VIN1 VIN2 ANALOG FRONT-END
Functional Diagram
10 DIGITAL DECODER 10 10 OUTPUT PROCESSING D9-D0 LLC
NONSTD VIDEO CLOCK
XTAL2
SDA SCL DEVADDR IRQ
I2C INTERFACE AND REGISTERS
MAX9526
________________________________________________________________ Maxim Integrated Products
1
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND .......................................................-0.3V to +2V DVDD to DGND ........................................................-0.3V to +2V DVDDIO to DGND .................................................-0.3V to +3.6V AGND to DGND.....................................................-0.1V to +0.1V D9-D0, LLC to DGND .........................-0.3V to (DVDDIO + 0.3V) VIN1, VIN2, VREF to AGND .......................-0.3V to (AVDD + 0.3V) XTAL/OSC, XTAL2 to AGND ....................................-0.3V to +2V IRQ, SDA, SCL, DEVADR to DGND ......................-0.3V to +3.6V Continuous Current In/Out All Pins ...................................50mA Continuous Power Dissipation (TA = +70C) 28-Pin QSOP Single-Layer Board (derate 10.8mW/C above +70C) .............................860mW 28-Pin QSOP Multilayer Board (derate 12.6mWC above +70C) ............................1009mW 32-Pin TQFN Multilayer Board (derate 20.8mW/C above +70C) ...........................1663mW Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = +1.8V, VDVDDIO = +3.3V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SUPPLIES Analog Supply Voltage Range Digital Supply Voltage Range Digital I/O Supply Voltage Range Analog Supply Current (Note 2) AVDD DVDD DVDDIO Normal operation IAVDD Sleep mode Shutdown Normal operation Digital Supply Current (Note 2) IDVDD Sleep mode Shutdown Normal operation, VDVDDIO = 1.8V Digital I/O Supply Current (Note 2) VIDEO INPUTS, VREF, AND CLAMP Input Voltage Range Input Resistance Input Capacitance Video Input Reference Voltage (VREF) Sync-Tip Clamp Level Input Clamping Current RIN CIN VREF VCLMP2 Activity detect clamp Activity detect clamp, VVIN = VCLMP2 + 150mV Guaranteed by full-scale conversion range 0.27 0.5 2 8 850 550 2.0 0.83 VP-P M pF mV mV A IDVDDIO Normal operation, VDVDDIO = 3.3V Sleep mode, VDVDDIO = 3.3V Shutdown, VDVDDIO = 3.3V 1.7 1.7 1.7 1.8 1.8 3.3 42 2.2 0.5 70 5 5 3.5 6.4 0.8 0.8 10 10 1.9 1.9 3.45 55 3 100 110 1000 1000 V V V mA A mA A mA A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Low-Power, High-Performance NTSC/PAL Video Decoder
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +1.8V, VDVDDIO = +3.3V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Sync Slice Comparator Level DC Restore Current DAC FullScale Range (Source and Sink) (Note 3) DC Restore Sync-Tip Level at VIN1/VIN2 ANALOG INPUT FILTER AND ADC (Note 4) Cutoff Frequency (3dB) Passband Flatness Stopband Cutoff Stopband Attenuation fSB f > fSB, VVIN = 0.65VP-P, reference level measured at 1MHz AGC disabled, gain programmed using I2C (ADAGC = 1), referenced to VIN1/VIN2 DNL INL AGCGAIN = 0x0 AGCGAIN = 0xF 670 270 0.167 AGCGAIN = 0x0, ADAGC = 1 AGCGAIN = 0x0, ADAGC = 1 Includes filter + ADC + digital anti-aliasing filter, input is -1dBFS; ADAGC = 1, AGCGAIN[3:0] = 0x0, defined as ratio of RMS signal to RMS noise in dB 1.7V < VAVDD < 1.9V, 1.7V < VDVDD < 1.9V VAVDD = 1.8V + 100mVP-P at 500kHz VAVDD = 1.8V + 100mVP-P at 3.58MHz VAVDD = 1.8V + 100mVP-P at 4.43MHz Differential Phase DP 5-step modulated staircase, f = 3.58MHz or 4.43MHz -67 dBFS -58 0.5 1 f3dB f < 5MHz, VVIN = 0.65VP-P, reference level measured at 1MHz 13 0.25 53 36 830 mVP-P 330 V/V LSB LSB MHz dB MHz dB SYMBOL Slow Medium Medium-fast (default) Fast AGCGAIN = 0x0, ADAGC = 1 AGCGAIN = 0xF, ADAGC = 1 CONDITIONS Activity detect slicer, referenced to VCLMP MIN TYP 50 3 6 12 24 0.51 0.72 V A MAX UNITS mV
MAX9526
Full-Scale Conversion Range
AGC Gain Stepsize Differential Nonlinearity Integral Nonlinearity
Signal-to-Noise Ratio
SNR
58.8
dB
-40
Power-Supply Rejection
PSR
ADAGC = 1 AGCGAIN[3:0] = 0x0 input level = 1MHz sine wave at -2dBFS
-57
1.0
degrees
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +1.8V, VDVDDIO = +3.3V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Differential Gain 2T Pulse Response 2T Bar Response SYMBOL DG CONDITIONS 5-step modulated staircase, f = 3.58MHz or 4.43MHz 2T = 200ns or 250ns Bar time is 18s, the beginning 2.5% and ending 2.5% of the bar time are ignored, 2T = 200ns or 250ns Bar time is 18s, the beginning 2.5% and ending 2.5% of the bar time are ignored, 2T = 200ns or 250ns 100kHz < f < 5MHz BWC BWL 5-step staircase LD FD Measured at the output regarding active video Measured at the output regarding active video MIN TYP 1 0.4 0.2 MAX UNITS % % %
2T Pulse to Bar Rating Group Delay Distortion Chroma Bandwidth Luma Bandwidth Luma Nonlinearity Luma Line Time Distortion (H-Tilt) Luma Field Time Distortion (V-Tilt) DIGITAL COMPOSITE DECODER Lock Time Horizontal Line Time Static Variation Maximum Horizontal Line Time Jitter (Async Mode) Maximum Horizontal Line Time Jitter (LLC mode) Line-Locked Clock Frequency Minimum Peak Signal to RMS Noise PLL Async Mode Jitter fLLC
0.2 1 1 5.5 1 0.5 0.1 3 -5 5 160 +5
% ns MHz MHz % % % frames % s ns MHz dB psRMS
DECODED LUMINANCE AND CHROMINANCE CHANNELS (Note 5)
Varies with input line rate Proper composite decoder operation Ideal input clock 000 001 010
27 23 20 180 250 375 500 750 1000 1500 2000
Line-Locked PLL Loop Bandwidth Set by Register 0x0E[2:0]
011 (default) 100 101 110 111
Hz
4
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Low-Power, High-Performance NTSC/PAL Video Decoder
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +1.8V, VDVDDIO = +3.3V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER CRYSTAL OSCILLATOR Frequency XTAL/OSC, XTAL2 Input Capacitance Maximum Load Capacitor Frequency Accuracy XTAL/OSC Logic-Low Threshold XTAL/OSC Logic-High Threshold XTAL/OSC Input Leakage Current Maximum Input Clock Jitter I2C SERIAL INTERFACE (Note 6) Serial-Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (REPEATED) START Condition SCL Pulse-Width Low SCL Pulse-Width High Setup Time for a REPEATED START Condition Data Hold Time Data Setup Time SDA and SCL Receiving Rise Time (Note 7) SDA and SCL Receiving Fall Time (Note 7) SDA Transmitting Fall Time (Note 7) Setup Time for STOP Condition Bus Capacitance Pulse Width of Suppressed Spike fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT tSU, DAT tR tF VDVDDIO = 3.3V VDVDDIO = 1.8V tSU, STO CB tSP IOL = 5mA, VDVDDIO = 3.3V IOL = 2mA, VDVDDIO = 1.7V 0 0.6 400 50 0.4 0.4 0 1.3 0.6 1.3 0.6 0.6 0 100 20 + 0.1CB 20 + 0.1CB 20 + 0.1CB 150 s pF ns 300 300 250 900 400 kHz s s s s s ns ns ns ns VIL VIH IIH, IIL XTAL oscillator disabled, clock input mode (XTAL_DIS = 1) XTAL oscillator disabled, clock input mode (XTAL_DIS = 1) XTAL oscillator disabled, clock input mode (XTAL_DIS = 1) 0.7 x VDVDD -10 0.01 500 +10 CXTAL, CXTAL2 CL1, CL2 Fundamental mode only 27.000 4 45 50 0.3 x VDVDD MHz pF pF ppm V V A psP-P SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX9526
tF
ns
HIGH-SPEED LOGIC OUTPUTS (D9-D0, LLC) Output Low Voltage VOL V
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = +1.8V, VDVDDIO = +3.3V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS IOH = 5mA, VDVDDIO = 3.3V Output High Voltage VOH IOH = 2mA, VDVDDIO = 1.7V Data to LLC Rising Edge Hold Time Data to LLC Rising Edge Setup Time Rise and Fall Time Output Leakage tHD tSU tR, tF IOH, IOL CL = 10pF, VDVDDIO = 1.8V CL = 25pF, VDVDDIO = 3.3V Outputs in high-impedance mode -10 MIN VDVDDIO x 0.8V V VDVDDIO 0.4V 13.5 13.5 18.5 18.5 3 3 0.01 +10 0.2 x VDVDDIO 0.4 0.01 10 0.3 x VDVDDIO 0.7 x VDVDDIO -10 AVDD = DVDD = DVDDIO = 0V -10 0.01 0.01 +10 +10 A 23.5 23.5 ns ns ns A TYP MAX UNITS
OPEN-DRAIN OUTPUTS (SDA and IRQ) Output Low Voltage Output High Current LOGIC INPUTS (SDA, SCL, DEVADR) Logic-Low Threshold Logic-High Threshold Input Leakage Current SDA/SCL Off Leakage Current VIL VIH IIH, IIL IIH V V A A VOL IOH IOL = 3mA, 1.7V < VDVDDIO < 2V IOL = 3mA, 2V < VDVDDIO < 3.3V VOUT = 3.3V V
Note 1: All devices are 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. Note 2: NTSC 75% color bar signal applied to video input. CL = 10pF on D9-D0 and LLC. External XTAL. Note 3: Internal test only. Digital core controls sync level adjustment current to adjust offset in analog signal path. Adjust level is based on value of sync level as converted by ADC. Digital core switches sourcing or sinking current into VIN1 or VIN2 nodes. Speed of correction (value of current) is controlled through I2C. Note 4: Filter and ADC performance measured using ADC outputs prior to composite digital demodulation (decoding). Note 5: Decoded luminance and chrominance specifications measured using entire signal path from video input to digital component outputs. Note 6: VDVDDIO = 1.8V and 3.3V. Note 7: CB is in pF.
6
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Low-Power, High-Performance NTSC/PAL Video Decoder
Typical Operating Characteristics
(VAVDD = VDVDD = +1.8V, VDVDDIO = 3.3V, VAGND = VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
FULL-SCALE CONVERSION RANGE
MAX9526 toc01
MAX9526
ANALOG INPUT FILTER RESPONSE
MAX9526 toc02
ADC EFFECTIVE NUMBER OF BITS vs. INPUT FREQUENCY
AGCGAIN = 0000 DIGITAL ANTI-ALIASING FILTER DISABLED
MAX9526 toc03
800 FULL-SCALE INPUT RANGE (mVP-P)
10.0 9.5 9.0 ENOB (LSB) 8.5 8.0
0
600
AMPLITUDE (dB)
-10
-20
400
-30 7.5 200 0 5 10 15 GAIN CODE (Reg0x0A[3:0]) (DECIMAL) -40 0.1 1 10 100 FREQUENCY (MHz) 7.0 0 2 4 6 FREQUENCY (MHz)
ADC SNR vs. GAIN CODE
MAX9526 toc04
DIGITAL COMPOSITE ANTI-ALIASING FILTER
MAX9526 toc05
DIGITAL Y FILTER
0 -10 AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 -80
MAX9526 toc06
60 59 58 57 SNR (dB) 56 55 54 53 52 51 50 0 5 10
10 0 -10 AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 -80
10
15
0
10
20
30
0
10
20
30
AGC GAIN CODE (REG0x0A[3:0]) (DECIMAL)
FREQUENCY (MHz)
FREQUENCY (MHz)
DIGITAL Cb/Cr FILTER
MAX9526 toc07
DIGITAL NOTCH FILTER
MAX9526 toc08
DECODED VIDEO OUTPUT 100% COLOR BARS (Y WAVEFORM)
MAX9526 toc09
10 0 -10 AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 -80 0 2 4 6 8 NTSC PAL
10 0 -10 AMPLITUDE (dB) -20 -30 -40 -50 -60 -70 -80 NTSC 0 2 4 FREQUENCY (MHz) PAL
1000
800 AMPLITUDE (LSB) 6 8
600
400
200
10
0 0 20 TIME (s) 40 60
FREQUENCY (MHz)
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = +1.8V, VDVDDIO = 3.3V, VAGND = VDGND = 0V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
DECODED VIDEO OUTPUT 100% COLOR BARS (Cb WAVEFORM)
MAX9526 toc10
DECODED VIDEO OUTPUT 100% COLOR BARS (Cr WAVEFORM)
MAX9526 toc11
OUTPUT CLOCK JITTER vs. PLL BANDWIDTH
3.5 OUTPUT CLOCK JITTER (ns) 3.0 2.5 2.0 1.5 1.0 0.5
MAX9526 toc12
1000
1000
4.0
800 AMPLITUDE (LSB)
800 AMPLITUDE (LSB)
600
600
400
400
200
200
0 0 20 TIME (s) 40 60
0 0 20 TIME (s) 40 60
0 0 500 1000 1500 2000 PLL BANDWIDTH (Hz)
OUTPUT CLOCK JITTER vs. VIDEO INPUT LEVEL
MAX9526 toc13
OUTPUT CLOCK JITTER vs. VIDEO INPUT SNR
MAX9526 toc14
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE
MAX9526 toc15
1.4 PLLBW = 180Hz 1.3 OUTPUT CLOCK JITTER (ns) 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.2 0.3 0.4 0.5 0.6
3.0 PLLBW = 180Hz 2.5 OUTPUT CLOCK JITTER (ns) 2.0 1.5 1.0 0.5 0
1000 DVDD SUPPLY CURRENT (A) 100 AVDD 10
ASYNC MODE
LLC MODE
1 DVDDIO 0.1
0.7
10
20
30
40
50
60
-40
0
40
80
120
VIDEO INPUT LEVEL (V)
TEMPERATURE (C)
TEMPERATURE (C)
VIDEO INPUT AND ADC OUTPUT 100% COLOR BARS
MAX9526 toc16
POWER-SUPPLY REJECTION vs. FREQUENCY
-45 AVDD = 1.8V + 100mVP-P
MAX9526 toc17
1.2 1.1 VIDEO INPUT (V) 1.0
1000
-40
800 ADC OUTPUT (LSB)
AMPLITUDE (dBFS)
-50 -55 -60 -65 -70 -75 -80 -85 AGCGAIN = 0000 AGCGAIN = 1111
600 0.9 0.8 0.7 200 0.6 0.5 0 10 20 30 40 50 60 70 TIME (s) 0 400
-90 0.01 0.1 1 10 FREQUENCY (MHz)
8
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Low-Power, High-Performance NTSC/PAL Video Decoder
Pin Description
PIN QSOP 1 2 3 4 5 6 7 8 9 10, 22 11, 23 12 13 TQFN-EP 30 31 32 1 2 3 4 5 6 7, 21 8, 22 10 11 NAME VIN1 VREF VIN2 AGND AVDD XTAL2 XTAL/OSC I.C. DEVADR DVDD DGND SDA SCL FUNCTION Single-Ended Composite Video Input 1. AC-couple the input video signal with a 0.1F capacitor. Video Reference Bypass. Bypass VREF to AGND with a 0.1F capacitor as close as possible to the device. Single-Ended Composite Video Input 2. AC-couple the input video signal with a 0.1F capacitor. Analog Ground Analog Power-Supply Input. Connect to a +1.8V supply. Bypass AVDD to AGND with a 0.1F capacitor. External Crystal. Connect XTAL2 to one terminal of the crystal oscillator. Ground XTAL2 when applying an external clock to XTAL/OSC. External Crystal/Oscillator. Connect XTAL/OSC to one terminal of a crystal or an external clock source. Connect XTAL2 to the other terminal of the crystal oscillator. Internal connection. Connect to DGND. I2C Device Address Select Input. Connect to DVDD, DGND, or SDA to select 1 of 3 available I2C slave addresses (see Table 5). Digital Power-Supply Input. Connect to a +1.8V supply. Bypass DVDD to DGND with a 0.1F capacitor in parallel with a 10F capacitor. Digital Ground. Connect both DGND terminals together. I2C-Compatible Serial-Data Input/Output. Connect a 10k pullup resistor from SDA to DVDDIO for full output swing. I2C-Compatible Serial-Clock Input. Connect a 10k pullup resistor from SCL to DVDDIO for full output swing. Hardware Interrupt Open-Drain Output. If not masked, IRQ is pulled low when the bits in the status register change state. Repeated faults have no effect on IRQ until IRQ is cleared by reading the corresponding status register. Connect a 10k pullup resistor from IRQ to DVDDIO for full output swing. Digital Video Outputs Bit 0-Bit 9, 10-Bit Component Digital Video Outputs. The output format is 10-bit ITU-R BT.656, 4:2:2 with embedded sync. D1 and D0 can be configured as horizontal and vertical sync outputs using the Clock and Output register 0x0D. D0 is LSB. Line-Locked 27MHz Clock Output. With line-locked mode, the LLC clock varies in response to horizontal line rate of the incoming video. In async mode, the LLC clock is synchronous to the crystal (see Table 1). Digital I/O Power-Supply Input. Accepts a +1.7V to +3.45V voltage input. Bypass to DGND with a 0.1F capacitor. No Connection. Not internally connected. Exposed Pad. EP is internally connected to GND. Connect EP to GND.
MAX9526
14
12
IRQ
15-20, 25-28
13-16, 18, 19, 24, 26, 27, 28
D0-D9
21
20
LLC
24 -- --
23 9, 17, 25, 29 --
DVDDIO N.C. EP
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Detailed Description
The MAX9526 is a simple, low-power video decoder that converts all modes of NTSC and PAL composite video signals to 10-bit YCbCr component video compatible with the ITU-R BT.656 standard. The device powers up in fully operational mode and automatically configures itself to standard NTSC or standard PAL. An internal 10-bit, 54MHz ADC samples at four times the sampling rate specified in ITU-R BT.601. The analog front-end of the MAX9526 features a DC restoration circuit, automatic gain control, and automatic offset correction. These blocks are controlled with digital processing to accurately optimize the full-scale range of the ADC. An integrated analog anti-aliasing filter eliminates the need for off-chip filtering. The device includes a 2:1 input multiplexer that can be configured to automatically select the input based on activity. The system clock is generated with an external 27MHz crystal and an internal oscillator. Optionally, a 27MHz or 54MHz external clock can be connected to the XTAL/OSC input. An internal line-locked digital PLL is used to generate the 54MHz ADC sample clock that is synchronous to the incoming video signal with up to 5% variation in horizontal line length. The digital output data and LLC clock are line locked to the video input and provide a standard ITU output. The PLL can also be configured to asynchronously sample the input using the crystal oscillator or external clock. The MAX9526 provides a 5-line adaptive comb filter to separate the luminance (Y) and chrominance (C) video components and reduce cross-chrominance and crossluminance artifacts. The MAX9526 operates with any type of standard composite video signal source including DVD players, video cameras, navigation systems, and VCRs. The device powers up in fully operational video decoder mode. An I2C register interface monitors status and enables programming of many decoder functions including brightness, contrast, saturation, and hue. The 10-bit output can be reconfigured to provide 8-bit data with separate horizontal and vertical syncs.
Analog Front-End (AFE)
The MAX9526 AFE implements DC restoration, automatic gain control (AGC), analog anti-aliasing filter (LPF), activity detection, channel selection, and analogto-digital conversion. A block diagram of the AFE is shown in Figure 1.
Activity Detect and Automatic Channel Selection The MAX9526 continuously monitors activity at both video inputs, VIN1 and VIN2. Activity on the selected channel is detected using the ADC output. On the unselected channel an analog sync-tip clamp and sync slicer are used to detect sync amplitudes greater than 50mV. In sleep mode, the analog sync-tip clamps and sync slicers are used to detect activity on both inputs, while the rest of the AFE is in a shutdown state. The output of the activity detect circuit is reported through the Status register 0x00. The user must manually select which video input to process by setting INSEL in register 0x09 appropriately.
The MAX9526 can optionally be configured to automatically select the video input that indicates the presence of activity by setting AUTOSEL = 1 in register 0x09. When activity is present on both V IN1 and V IN2 at power-up or when there is no activity on either input channel, VIN1 is selected. When there is activity on VIN2 and there is no activity on VIN1, then VIN2 is selected. When VIN2 is automatically selected with the presence of activity, the input only switches to VIN1 when activity goes away on VIN2.
ACTIVITY DETECT DC RESTORATION DAC
DIGITAL CONTROL
VIN1 VIN2 VREF INTERNAL BIAS ANALOG AGC ANALOG LPF 10-BIT ADC
10
DIGITAL FILTERING
10 TO DECODER
Figure 1. Analog Front-End
10 ______________________________________________________________________________________
Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
FROM AFE 10 SYNC PROCESSING CLOCK GENERATOR AND PLL
NONSTD VIDEO
XTAL/OSC OSCILLATOR XTAL2
MUX MUX
CLOCK
Figure 2. Sync Processing, Clock Generation, and PLL
VREF Generation A differential signal path is used to process the analog video signal to minimize the effect of noise coupling. A DC reference (VREF) of 850mV is internally generated and decoupled externally with a 0.1F capacitor. Identical signal paths and video buffers are used for both the selected video input and the video reference voltage. The signals are converted to a fully differential signal by the analog AGC circuit. DC Restoration DAC The video inputs, VIN1 and VIN2, are AC-coupled to the MAX9526 with 0.1F capacitors. The DC restoration circuit sets the sync level at the output of the ADC by sinking or sourcing current at the selected video input. A digital control at the ADC output is used to monitor the average sync level. An error signal is generated in the digital control block that is used by a current DAC to source or sink current to the AC-coupled input to restore the DC level. The DC restoration circuit also corrects the offset in the analog signal chain and sets the sync level at the ADC output to code 32 (decimal). Analog Automatic Gain Control (Analog AGC) The MAX9526 includes an analog variable-gain amplifier with a digitally controlled gain for automatic gain control (AGC). The AGC uses the sync amplitude at the output of the ADC to control the gain. For signals without copy protection, the AGC adjusts the gain until the sync amplitude is 208 (decimal) codes at the ADC output. For inputs with copy protection, the AGC automatically compensates for the reduced sync amplitude on active lines.
The analog AGC loop can be disabled and the gain is set manually to 1 of 16 values using the Gain Control register 0x0A. The range of analog gain is 3.5dB to 12dB.
Analog Lowpass Filter (LPF) The MAX9526 includes a high-performance anti-aliasing analog lowpass filter with a 3dB bandwidth of 13MHz (typ) and better than 0.25dB (typ) passband flatness to 5MHz. This eliminates the need for external filtering on the video inputs. The filter typically provides 36dB attenuation at 53MHz (1MHz below ADC sample rate). 54Msps Video ADC A 10-bit, 54Msps ADC converts the filtered analog composite video signal for digital signal processing (composite video demodulation). Digital Filtering Digital filtering at the ADC output removes any out-ofband interference and improves the signal-to-noise ratio before decoding. The signal path includes a digital anti-aliasing lowpass filter that has 1dB of passband flatness to 5.5MHz and a minimum of 45dB of stopband attenuation for frequencies greater than 9MHz.
Sync Processing, Clock Generation, and PLL
The sync processing, clock generation, and PLL extract the timing information from incoming video and generate the clock for the rest of the chip. Figure 2 shows the block diagram for this block.
Crystal Oscillator/Clock Input The MAX9526 includes a low-jitter crystal oscillator circuit optimized for use with an external 27MHz crystal. The device also accepts an external CMOS logic-level clock at either 27MHz or 54MHz. To use an external clock (27MHz or 54MHz) instead of a crystal, set XTAL_DIS = 1 in register 0x0D. To use a 54MHz external clock instead of a 27MHz clock, SEL_54MHz must also be set to 1 in register 0x0D.
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11
Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Sync Processing The sync processing block extracts the sync information and automatically detects 525 line or 625 line inputs. Clock Generator and PLL The PLL operates in either line-locked clock (LLC) mode or async mode. Selection of the mode is controlled automatically by the MAX9526 or can optionally be overwritten with the LLC_MODE bits in PLL Control register 0x0E. In LLC mode, a hybrid analog/digital PLL generates a low-jitter line-locked clock. The 54MHz sample clock is synchronous to the input video. The LLC clock output is also synchronous to the input video. The ITU output has the correct number of samples per line and lines per field. The PLL is designed to lock to signals with up to 160ns peak jitter. When the jitter exceeds the 160ns peak, the PLL coasts until the jitter improves. If the jitter continuously exceeds the 160ns peak, the PLL relocks and the HLOCK status bit in register 0x00 is set to 0.
In LLC mode, the bandwidth of the PLL can be optionally programmed to one of eight values between 180Hz and 2000Hz using the PLLBW bits in PLL Control register 0x0E. The default value for the PLL bandwidth is 500Hz. In async mode, the sample clock frequency is generated by multiplying the crystal frequency by a factor of two and the video signal is sampled asynchronously with the 2x crystal clock. To eliminate artifacts, the MAX9526 uses an adaptive poly-phase filter to correct timing and phase errors introduced by the asynchronous sampling. The LLC output is generated by dividing the 54MHz sampling clock by two. The ITU output in async mode has the correct number of lines per frame and the correct number of pixels per line except on the first line of each field. The timing correction block uses this line to compensate for timing errors between the incoming video signal and the crystal. As a result, the first line of each field is longer or shorter for several pixels depending on the magnitude of the frequency difference between the incoming video signal and the local crystal. For example, a 100ppm frequency difference between the incoming video signal and the crystal results in approximately 23 extra or fewer pixels on the first line of each field. Line length errors on line one are of no consequence for most applications since it is in the vertical blanking interval and does not contain active video or any other type of data. The types of inputs that cause the PLL to automatically switch to async mode are video inputs with a nonstandard carrier frequency. For standard video, the carrier frequency is always a precise multiple of the horizontal frequency. A typical nonstandard input is video cassette recorders in which the carrier is not a precise multiple of the horizontal frequency. The nonstandard detect (NONSTD) status from the decoder is used to automatically switch the PLL to async mode when nonstandard carrier frequencies are detected. The NONSTD status is monitored in the Status register 0x00.
Clocking Modes In addition to automatic configuration, the MAX9526 can also be manually configured to provide maximum flexibility in setting the clock inputs and outputs of the chip. Table 1 summarizes the clocking modes that are supported.
Digital Composite Decoding
Figure 3 shows a block diagram of the digital composite decoder. This block converts the digitized composite video signal to digital component video.
Sync Level Correction and Sync Extraction The sync extraction function extracts the raw sync signals from the video and the extracted sync information is sent to the sync processor. The sync level from the AFE is code 32 (decimal) on a 10-bit scale and the blanking level is approximately 208 (decimal) codes above the sync level. The sync slicer default threshold is set to approximately the middle of the sync pulse at decimal code 128. The sync slice level can optionally be manually adjusted using the slice bits in register 0x0F.
The sync level correction block features an optional digital clamp that can be enabled in register 0x09. Enabling the digital clamp sets the sync level to code 0 (decimal) and gives higher frequency tracking of the input signals. When the digital clamp is enabled, the sync slice level in register 0x0F should be adjusted accordingly to provide equivalent noise rejection.
Sync Processor and Analog Copy Protection Detection The sync processor extracts the horizontal sync and vertical sync signals. Field pulses and burst gate pulses are generated based on VSYNC and HSYNC, respectively. The sync processing block provides sync timing to measure the sync level and amplitude for the black level control and composite AGC. The sync processor also detects incoming video signal standards (525 line NTSC and 625 line PAL). Video standard information is available in Status register 0x01. The detected video standard is used to automatically configure the decoder. The MAX9526 detects NTSC-M (standard NTSC) and PAL B/G/H/I/D (standard PAL)
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
FROM ANALOG FRONT-END
10
SYNC-LEVEL CORRECTION AND SYNC EXTRACTION
COMPOSITE AGC ADAPTIVE COMB FILTER CHROMA AGC NTSC/PAL
Y-DELAY CHROMINANCE DEMODULATOR
Y/Cb/Cr FILTERS
Y
LINE DELAYS
Cb LPF Cr LPF TIMING INFO
SYNC PROCESSOR AND ANALOG COPY PROTECTION DETECT NONSTD VIDEO
NONSTD VIDEO HORZ, VERT, FRAME
Figure 3. Digital Composite Decoding Functional Diagram
standards automatically. See the Standard Select, Shutdown, and Control Register section for manual programming. The sync processor block also detects analog copy protection. Extracted copy protection information is available in Status register 0x01.
Output Formatting
Figure 4 shows the output formatting section of the MAX9526.
Image Enhancement and Color Correction The MAX9526 provides contrast, brightness, hue, and saturation manual control in registers 0x05 to 0x08. Time Base Correction The MAX9526 provides time base correction (TBC) to allow the decoder to properly process unstable and nonstandard video from sources such as a VCR. The time base correction minimizes the effect of sampling jitter to ensure that there are a correct number of pixels per active line. Test Pattern Insertion The MAX9526 automatically outputs a black screen when there is no video at the inputs. The test pattern can also be configured to provide a blue screen, 75% color bars, or 100% color bars through register 0x0C. Timing Reference Signal Insertion and ITU-R BT.656 Encoding The MAX9526 multiplexes the Y, Cr, and Cb signals with an embedded timing reference signal conforming to the ITU-R BT.656 standard. SAV and EAV sequences are inserted into the data stream to indicate the active video time in ITU-R BT.656 format. The output timing insertion is illustrated in Figure 5. The SAV and EAV sequences are shown in Table 2. Output Timing The output setup and hold diagram is shown in Figure 6.
13
Composite Automatic Gain Control (AGC) In addition to the analog AGC that optimizes the ADC full-scale range, a digital AGC is used to more accurately set the video amplitude. The Composite AGC uses the amplitude of the sync signal to set the gain. Adaptive Comb Filter The MAX9526 uses a 5-line adaptive comb filter to separate luminance and chrominance components from a single composite channel. The adaptation algorithm does not require configuration. The adaptive comb filter adjusts based on the relationship and content of video data between neighboring lines. The filter automatically adapts the comb filter structure between a 5-line filter and a notch filter. Chrominance Signal Demodulator After luminance (Y) and chrominance (C) components are separated, the Y component passes through a delay line to compensate for the C component delay through the demodulator. The chrominance signal path contains an AGC before the signal demodulator. The chrominance AGC uses the color burst amplitude to set the gain. The chrominance is demodulated using a subcarrier signal locked to the burst. The demodulated chrominance signals, Cb and Cr, are lowpass filtered to eliminate unwanted products of demodulation.
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Table 1. MAX9526 Clock Mode Summary
SEL XTAL_DIS PLLBYP LLC_MODE _54MHz REGISTER 0x0D REGISTER 0x0E REGISTER 0x0E REGISTER 0x0D B3 B3 B5-4 B4 CLOCK MODE DESCRIPTION
0
0
0
00
Input clock = 27MHz crystal. Sample clock = line locked or async (autodetected). This is the default power-up mode for the MAX9526. Input clock = 27MHz crystal. Sample clock = line locked (forced on). Input clock = 27MHz crystal. Sample clock = 2x input clock. Invalid modes. The PLL can only be bypassed if the input clock is 54MHz. Input clock = 27MHz external clock. Sample clock = line locked or async (autodetected). Input clock = 27MHz external clock. Sample clock = line locked (forced on). Input clock = 27MHz external clock. Sample clock = 2x input clock. Invalid mode. 54MHz crystal not supported. Input clock = 54MHz external clock. Sample clock = line locked or async (autodetected). Input clock = 54MHz external clock. Sample clock = line locked (forced on). Input clock = 54MHz external clock. Sample clock = input clock divided by 2, then multiplied by 2x through the PLL. This mode uses the PLL to filter high-frequency jitter on the input source. Invalid mode. The PLL can only be bypassed when the output is not a line-locked clock. Input clock = 54MHz external clock. Sample clock = input clock. Use this mode when a low-jitter, 54MHz input clock is used.
0 0 0 0 0 0 1 1 1
0 0 X 1 1 1 0 1 1
0 0 1 0 0 0 X 0 0
10 11 XX 00 10 11 XX 00 10
1
1
0
11
1
1
1
X0
1
1
1
11
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
10 Y Cb Cr IMAGE ENHANCEMENT AND COLOR CORRECTION TIME BASE CORRECTION TEST PATTERN INSERTION TIMING REFERENCE SIGNAL INSERTION/ ITU ENCODING D9-D0 LLC
TIMING INFO
HORZ, VERT, FRAME
Figure 4. Digital Output Processing
Table 2. ITU-R BT.656 SAV and EAV Code Sequence
CONDITION FIELD Even Even Even Even Odd Odd Odd Odd V TIME Blank Blank Active Active Blank Blank Active Active H TIME EAV SAV EAV SAV EAV SAV EAV SAV F 1 1 1 1 0 0 0 0 FVH V 1 1 0 0 1 1 0 0 H 1 0 1 0 1 0 1 0 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF VALUE SAV/EAV CODE SEQUENCE FIRST SECOND 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 THIRD 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 TRS 0xF1 0xEC 0xDA 0xC7 0xB6 0xAB 0x9D 0x80
CLKP
VD[7:0]
FFh 00h 00h EAV CODE
XY
80h 16h
80h 160h FFh 00h 00h XYh Cb0 SAV CODE
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
HACTIVE
Figure 5. Timing Diagram of ITU-R BT.656 Format
D9-D0 tSU LLC tHD
Figure 6. Output Setup and Hold
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
CVBS INPUT 1 37.5 0.1F VIN 37.5 I2C IF MAX9526 XTAL/OSC DOUT LLC ITU-1 27MHz
CVBS INPUT 2 37.5 0.1F VIN 37.5 I2 C IF MAX9526 XTAL/OSC DOUT LLC ITU-2 27MHz 4-TO-1 PIXEL LEVEL MULTIPLEXER AND CHANNEL ID INSERTER 0.1F VIN 37.5 I2 C IF MAX9526 XTAL/OSC DOUT LLC ITU-3 27MHz CTRL [0] CTRL [1]
4-CHANNEL VIDEO MUX
CVBS INPUT 3 37.5
CVBS INPUT 4 37.5 0.1F VIN 37.5 I2 C IF MAX9526 XTAL/OSC DOUT LLC ITU-4 27MHz
SDA SCL I2C INTERFACE
Q OSCILLATOR 27MHz
x4
108MHz CLOCK
Figure 7. Multiple Video Input Processing
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
+3.3V OR +1.8V FB 0.1F 10F 0.1F 0.1F 10F +1.8V 0.1F 10F
CVBS INPUT 1
37.5
0.1F
AVDD VIN1
DVDD
DVDDIO LLC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDDIO 10k CLK 27MHz D9 D8 D7 D6 D5 PARALLEL OUTPUT D4 D3 D2 D1 D0
37.5 0.1F
VREF
CVBS INPUT 2
37.5
0.1F VIN2
MAX9526
37.5
DVDDIO
IRQ 47pF
IRQ
10k SDA SCL ADDR
10k SDA SCL DEVADR I2C INTERFACE I.C. AGND
XTAL/OSC 1M* XTAL2 DGND 47pF GND 27MHz
*OPTIONAL
Figure 8. MAX9526 Typical Application Circuit with Additional Supply Isolation
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Table 3. Recommended Crystal Parameters
PARAMETER Frequency Maximum Crystal ESR Accuracy Room temperature Line-locked mode Async mode with multiple decoders CONDITIONS Fundamental mode only MIN TYP 27.000 30 50 50 MAX UNITS MHz ppm
Applications Information
Multiple Decoder Operation
Multiple asynchronous video input signals can be decoded synchronously using multiple MAX9526s in asynchronous (async) sampling mode. Figure 7 shows an example of decoding four video input signals. The MAX9526 is configured for async sampling mode by writing the following registers: Register 0x0D, B3 (XTAL_DIS) = 1 (disables the crystal oscillator) Register 0x0E, B5-4 (LLC_MODE) = 11 (forces sampling to async mode) When the MAX9526 is in async sampling mode, the data outputs, D9-D0, of all decoders are synchronous with the input clock (XTAL/OSC). The video content in the data outputs is not frame aligned because the video sources into each MAX9526 is asynchronous. A small FPGA can be implemented to multiplex all four channels into a single 8- or 10-bit bus. This FPGA can also format the outputs to be compatible for input into a compression processor, which is commonly used in digital video recorders (DVRs). The crystal oscillator (external or internal) must have better than 50ppm accuracy for acceptable decoding in this mode. An accuracy of 10ppm is recommended for optimal performance.
I2C Serial Interface
The MAX9526 features an 2-wire serial interface consisting of a serial-data line (SDA) and a serial-clock line (SCL). SDA and SCL facilitate communication between the MAX9526 and the master at clock rates up to 400kHz. Figure 9 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. The master device writes data to the MAX9526 by transmitting the proper slave address followed by the register address and then the data word. Each transmit sequence is framed by a START (S) or REPEATED START (Sr) condition and a STOP (P) condition. Each word transmitted to the MAX9526 is 8 bits long and is followed by an acknowledge clock pulse. A master reading data from the MAX9526 transmits the proper slave address followed by a series of nine SCL pulses. The MAX9526 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START or REPEATED START condition, a not acknowledge, and a STOP condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on SDA. SCL operates only as an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the single master has an opendrain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9526 from high-voltage spikes on the bus lines, as well as minimize crosstalk and undershoot of the bus signals. I2C/SMBusTM-compatible,
Recommended Crystal Parameters
Recommended crystal parameters are shown in Table 3.
Power-Supply Decoupling
For systems where additional power-supply isolation is required, the circuit shown in Figure 8 can be used. Additional supply decoupling is added and analog power (AVDD) isolation is increased with the use of a ferrite bead (FB). The analog ground connection (AGND) should be connected to a separate ground plane that has a small bridge to the main ground plane of the system. The video input termination (VIN1/VIN2), video reference (VREF) decoupling, and AVDD supply decoupling should also be connected to the AGND ground plane.
SMBus is a trademark of Intel Corp.
18
Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high
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Low-Power, High-Performance NTSC/PAL Video Decoder
transition on SDA while SCL is high (Figure 10). A START condition from the master signals the beginning of a transmission to the MAX9526. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX9526 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9526, followed by a STOP condition.
MAX9526
Early STOP Conditions The MAX9526 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the seven most significant bits (MSBs) followed by the read/write bit. For DEVADR connected to DGND, setting the read/write bit to 1 (slave address = 0x43) configures the MAX9526 for read mode. Setting the read/write bit to 0 (slave address = 0x42) configures the MAX9526 for write mode. The address is the first byte of information sent to the MAX9526 after the START condition. The MAX9526 slave address is configurable with DEVADR. Table 5 shows the addresses of the MAX9526. Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9526 uses to handshake receipt each byte of data when in write mode (see Figure 11). The MAX9526 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master retries communication. The master pulls
Write Data Format A write to the MAX9526 includes transmission of a START condition, the slave address with the R/W bit set to 0, one byte of data to configure the internal register address pointer, one or more bytes of data, and a STOP condition. Figure 12 illustrates the proper frame format for writing one byte of data to the MAX9526. Figure 13 illustrates the frame format for writing n bytes of data to the MAX9526. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9526. The MAX9526 acknowledges receipt of the address byte during the master-generated 9th SCL pulse. The second byte transmitted from the master configures the MAX9526's internal register address pointer. The pointer tells the MAX9526 where to write the next byte of data. An acknowledge pulse is sent by the MAX9526 upon receipt of the address pointer data. The third byte sent to the MAX9526 contains the data that is written to the chosen register. An acknowledge pulse from the MAX9526 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential registers within one continuous frame. Figure 13 illustrates how to write to multiple registers with one frame. The master signals the end of transmission by issuing a STOP condition.
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19
Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tBUF tHD, STA tSP tSU, STO
Figure 9. I2C Serial Interface Timing Diagram
S
Sr
P
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
SCL 1 2 8 NOT ACKNOWLEDGE 9
SDA
SDA ACKNOWLEDGE
Figure 10. START, STOP, and REPEATED START Conditions
Figure 11. Acknowledge
Read Data Format Send the slave address with the R/W bit set to 1 to initiate a read operation. The MAX9526 acknowledges receipt of its slave address by pulling SDA low during the 9th SCL clock pulse. A START command followed by a read command resets the address pointer to register 0x00.
The first byte transmitted from the MAX9526 is the contents of register 0x00. Transmitted data is valid on the rising edge of SCL. The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read is from register 0x00.
The address pointer can be preset to a specific register before a read command is issued. The master presets the address pointer by first sending the MAX9526's slave address with the R/W bit set to 0 followed by the register address. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9526 then transmits the contents of the specified register. The address pointer autoincrements after transmitting the first byte. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figure 14 illustrates the frame format for reading one byte from the MAX9526. Figure 15 illustrates the frame format for reading multiple bytes from the MAX9526.
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
ACKNOWLEDGE FROM MAX9526 B7 ACKNOWLEDGE FROM MAX9526 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9526 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
Figure 12. Writing a Byte of Data to the MAX9526
ACKNOWLEDGE FROM MAX9526 ACKNOWLEDGE FROM MAX9526 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9526 REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 ACKNOWLEDGE FROM MAX9526 B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE 1 1 BYTE
A
DATA BYTE n 1 BYTE
A
P
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
Figure 13. Writing n Bytes of Data to the MAX9526
NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9526 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9526 REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9526 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 14. Reading One Indexed Byte of Data from the MAX9526
ACKNOWLEDGE FROM MAX9526 S SLAVE ADDRESS R/W 0 A
ACKNOWLEDGE FROM MAX9526 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX9526 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 15. Reading n Bytes of Indexed Data from the MAX9526
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Programming the MAX9526
I2C Register Map Table 4 shows an I2C register map. All static bits should not be programmed to any values other than the default value listed in Table 4.
Table 4. Register Map Overview
REGISTER Status 0 Status 1 IRQ MASK 0 IRQ MASK 1 Standard Select, Shutdown, and Control Contrast Brightness Hue Saturation Video Input Select and Clamp Gain Control Color Kill Output Test Signal Clock and Output PLL Control Miscellaneous AUTOSEL CRAGC BW RAWADC 0 0 0 INSEL CMPAGC CRKDIS 0 CLIP 0 0 B7 VID1 0 IVID1 0 B6 VID2 L525 IVID2 IL525 STDSEL B5 0 0 0 0 B4 CTHR 0 ICTHR 0 AUTOD B3 ADCOVR 0 0 SHDN B2 HLOCK 0 0 RESET B1 NONSTD 0 0 SLEEP B0 LSTLCK ACP IACP RESET_S REG ADDR 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0 0 D_CLMP_ DIS ADCGAIN CTHRSH TGSRC XTAL_DIS PLLBYP SSLICE 0 HSVS CBAR DATAZ PLLBW LLCZ 0 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F POWERON STATE n/a n/a 0x00 0x00 0x10 0x80 0x00 0x80 0x88 0x02 0x00 0x23 0x00 0x00 0x03 0x18
IADCOVR IHLOCK
INONSTD ILSTLCK
CONT BRIGHT HUE SATU DCRESTORE_RANGE 0 1 TGEnab LLC_INV ADAGC 0 TGTIM SEL_54 MHZ 1
LLC_MODE DISAAFLT
Table 5. I2C Slave Address
ADDRESS CONNECTION (DEVADR) DVDD DGND SDA WRITE ADDRESS 0x40 0x42 0x44 READ ADDRESS 0x41 0x43 0x45
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Low-Power, High-Performance NTSC/PAL Video Decoder
I2C Bit Descriptions
Status Register 0
REG 0x00 B7 VID1 B6 VID2 B5 0 B4 CTHR B3 ADCOVR B2 HLOCK B1 NONSTD B0 LSTLCK
MAX9526
Video Input 1 Active (VID1) 1 = Active video detected at VIN1. 0 = No active video detected on VIN1. Video Input 2 Active (VID2) 1 = Active video detected at VIN2. 0 = No active video detected on VIN2. Below Color Kill Threshold (CTHR) 1 = Color carrier has fallen below color kill threshold since last register 0 read. 0 = Color carrier has not fallen below color kill threshold since last register 0 read. CTHR reports when the chroma carrier is below color kill threshold. See register 0x0B for color kill threshold and color kill enable settings. ADC Out-of-Range (ADCOVR) 1 = ADC has gone outside the full-scale range since last register 0 read. 0 = ADC has not gone outside the full-scale range since last register 0 read. ADCOVR triggers when the ADC input is above or below the ADC input range. This bit is cleared after reading status register 0. ADCOVR is not triggered on lines during the vertical blanking interval, on lines at the start or end of the field that may have pulses from copy protection, or on lines that may have ancillary data.
Horizontal Lock (HLOCK) 1 = Line-locked PLL is locked to horizontal line rate and has not lost lock since last status register 0 read.
0 = Line-locked PLL has lost lock since last status register 0 read.
Nonstandard Video (NONSTD) 1 = Nonstandard video detected. 0 = Standard video format detected.
For standard video, the carrier frequency is always a precise multiple of the horizontal frequency. An example of nonstandard inputs are video cassette recorders in which the carrier is not a precise multiple of the horizontal frequency.
Demodulator Lost Lock (LSTLCK) 1 = Demodulator has lost lock since last status register 0 read. 0 = Demodulator has maintained lock since last status register 0 read.
Status Register 1
REG 0x01 B7 0 B6 L525 B5 0 B4 0 B3 0 B2 0 B1 0 B0 ACP
525 Line Mode (L525)
1 = 525 line video detected. 0 = 625 line video detected. This output is only valid when the decoder is locked and operating normally.
Analog Copy Protection (ACP) 1 = Analog copy protection detected.
0 = No analog copy protection detected.
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Interrupt Mask Register 0
REG 0x02 B7 IVID1 B6 IVID2 B5 0 B4 ICTHR B3 IADCOVR B2 IHLOCK B1 INONSTD B0 ILSTLCK
Active Video 1 Interrupt (IVID1) 1 = Change in VID1 bit status triggers a hardware interrupt.
0 = No interrupt on VID1 changes (default). See register 0x00, B7.
Horizontal Lock Interrupt Enable (IHLOCK) 1 = Change in HLOCK bit from 1 to 0 triggers a hardware interrupt.
0 = No interrupt on HLOCK changes (default). See register 0x00, B2.
Active Video 2 Interrupt (IVID2) 1 = Change in VID2 bit status triggers a hardware interrupt. 0 = No interrupt on VID2 changes (default).
See register 0x00, B6.
Nonstandard Video Interrupt Enable (INONSTD) 1 = Change in NONSTD bit from 0 to 1 triggers a hardware interrupt. 0 = No interrupt on NONSTD changes (default).
See register 0x00, B1.
Color Kill Threshold Interrupt (ICTHR) 1 = Transition in CTHR bit from 0 to 1 triggers a hardware interrupt. 0 = No interrupt on CTHR changes (default).
See register 0x00, B4.
Demodulator Lock Interrupt Enable (ILSTLCK) 1 = Change in LSTLCK bit from 0 to 1 triggers a hardware interrupt. 0 = No interrupt on LSTLCK changes (default).
See register 0x00, B0.
ADC Out-of-Range Interrupt Enable (IADCOVR) 1 = Change in ADCOVR bit from 0 to 1 triggers a hardware interrupt. 0 = No interrupt on ADCOVR changes (default).
See register 0x00, B3.
Interrupt Mask Register 1
REG 0x03 B7 0 B6 IL525 B5 0 B4 0 B3 0 B2 0 B1 0 B0 IACP
525 Line Video Interrupt Enable (IL525) 1 = Change in L525 bit status triggers a hardware interrupt. 0 = No interrupt on L525 changes (default). This interrupt is masked by the HLOCK and LSTLCK status. Changes in the L525 status triggers a hardware interrupt only when HLOCK = 1 and LSTLCK = 0. See register 0x01, B6.
Analog Copy Protection Interrupt Enable (IACP) 1 = Any change in ACP status bit (register 0x01, B0) triggers a hardware interrupt. 0 = No interrupt on analog copy protection changes (default). See register 0x01, B0.
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Low-Power, High-Performance NTSC/PAL Video Decoder
Standard Select, Shutdown, and Control Register
REG 0x04 B7 B6 STDSEL B5 B4 AUTOD B3 SHDN B2 RESET B1 SLEEP B0 RESET_S
MAX9526
Video Standard Select (STDSEL) Bit B7 (TYPE) 1 = NTSC J, PAL 60, NTSC 4.43. 0 = NTSC M (standard NTSC), PAL M, PAL B/G/H/I/D (standard PAL), PAL Combination N (default). Bit B6 (525 Line) 1 = 525 line video. 0 = 625 line video (or NTSC 4.43) (default).
Bit B6 sets the video line rate when AUTOD = 0. When AUTOD = 1 (default), B6 is ignored.
Standard Autodetect (AUTOD) 1 = Automatically detects 525 vs. 625 line video (default).
0 = Manually programs 525 vs. 625 line video. Autodetect function can only be used to distinguish between standard PAL and standard NTSC. The autodetect function requires register 0x04, B7 = B5 = 0.
Bit B5 (Unconventional Video) 1 = PAL Combination N, PAL M, NTSC 4.43, PAL 60. 0 = PAL B/G/H/I/D (standard PAL), NTSC M (standard NSTC), or NTSC J (default).
The 3 bits in the STDSEL register can be used to program the expected input video format. Bit B6 (525 vs. 625 line video) can be automatically set by using the autodetect function (see AUTOD bit description, register 0x04, B4).
Low-Power Shutdown (SHDN) 1 = Low-power shutdown mode. 0 = Normal operation (default).
In shutdown, all logic outputs are low (unless programmed to high impedance using register 0x0D, B1). I2C register contents are retained during shutdown.
System Reset (RESET) 1 = All registers and system state returned to power-on default conditions. 0 = Normal operation (default).
Because all registers' contents are set to power-on default state, this bit clears itself after being written.
B[7:5]
000: 001: 010: 011: 100: 101: 110: 111: PAL B/G/H/I/D (standard PAL) PAL Combination N NTSC M (standard NTSC) PAL M N/A NTSC 4.43 NTSC J PAL60
Sleep Mode (SLEEP)
1 = Low-power sleep mode. 0 = Normal operation (default). In sleep mode, all logic outputs are low (unless programmed to high impedance using register 0x0D, B1). I2C register contents are retained. Video activity detect is still active. Activity status is available in register 0x00.
Soft Reset (RESET_S) This bit resets everything on the device except the register values. This bit is self-clearing. 1 = Soft reset. 0 = Normal operation (default).
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Contrast Control Register
REG 0x05 B7 B6 B5 B4 CONT B3 B2 B1 B0
Contrast (CONT) 0x00 = Luma gain is 0. 0x80 = Luma gain is 1 (default). 0xFF = Luma gain is 255/128, or approximately 2.
When ACP is detected (register 0x01, B0), 15 (decimal) is subtracted from CONT.
Brightness Control Register
REG 0x06 B7 B6 B5 B4 BRIGHT B3 B2 B1 B0
Brightness (BRIGHT) 0x00 = Luma offset is 0 IRE (default). 0x7F = Luma offset is +75.66 IRE.
0x80 = Luma offset is -76.22 IRE.
Hue Control Register
REG 0x07 B7 B6 B5 B4 HUE B3 B2 B1 B0
Hue (HUE) 0x80 = Chroma phase is 0 degrees with respect to color burst (default). 0xFF = Chroma phase is approximately +45 degrees with respect to color burst. 0x00 = Chroma phase is -45 degrees with respect to color burst.
Saturation Control Register
REG 0x08 B7 B6 B5 B4 SATU B3 B2 B1 B0
Saturation (SATU)
0x00 = Chroma gain is 0. 0x80 = Chroma gain is 1. 0x88 = Default. 0xFF = Chroma gain is 255/128, or approximately 2. When ACP is detected (register 0x01, B0), 8 (decimal) is added to SATU.
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Low-Power, High-Performance NTSC/PAL Video Decoder
Video Input Select and Clamp Control Register
REG 0x09 B7 AUTOSEL B6 INSEL B5 B4 B3 0 B2 0 B1 D_CLMP_DIS B0 0
MAX9526
DCRESTORE_RANGE
Video Auto-Select (AUTOSEL) 1 = Automatically selects video input with activity detect. When activity is present on both or neither VIN1 and VIN2 after a reset (POR, register reset, sleep mode, shutdown), VIN1 is selected. If there is activity on VIN2 and no activity on VIN1, then VIN2 is selected. When V IN2 is automatically selected with the presence of activity, the input switches to VIN1 only when activity goes away on VIN2. 0 = Video input is selected manually (default).
See INSEL (register 0x09, B6) for manual input selection.
Analog DC Restoration Current Range (DCRESTORE_RANGE) This bit sets the full-scale range of the DC restoration DAC. Increasing the full-scale current range increases the bandwidth and range of the DC restoration loop. 10 = Slow (3A into video input coupling capacitor) 11 = Medium (6A into video input coupling capacitor) 00 = Medium-fast (12A into video input coupling capacitor) (default) 01 = Fast (24A into video input coupling capacitor) Digital Clamp Disable (D_CLMP_DIS) This bit disables the digital clamp. 1 = Disables digital sync-tip clamp (default).
0 = Enables digital sync-tip clamp. Enabling the digital clamp sets the sync level to code 0 (decimal) and gives higher frequency tracking of input signals. If the digital clamp is enabled, the sync slice level in register 0x0F should be adjusted accordingly to provide equivalent noise rejection. Typically, SSLICE[3:0] should be reduced by 2 LSBs when D_CLMP_DIS is set to 1.
Manual Video Input Select (INSEL) 1 = Select VIN2. 0 = Select VIN1 (default).
Video autoselect bit (AUTOSEL) must be 0 for this register to take effect.
Gain-Control Register
REG 0x0A B7 CRAGC B6 CMPAGC B5 0 B4 ADAGC B3 B2 AGCGAIN B1 B0
Chrominance AGC Disable (CRAGC) 1 = Chroma gain is frozen. 0 = Automatic chroma gain is based on color burst level (default). To freeze the chroma gain at the default value of 17 (hex), set CRAGC = 1 and apply a soft reset. Composite AGC Disable (CMPAGC) 1 = Digital composite gain frozen at default value (80 (hex)).
0 = Automatic digital composite gain based on sync level (default).
Disable Analog Automatic Gain Control (ADAGC) 1 = Analog automatic gain control is disabled. 0 = Analog automatic gain control is enabled (default). The analog automatic gain-control (AGC) loop adjusts the AGC gain to optimally use the available ADC fullscale range.
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Analog AGC Gain (AGCGAIN) This bit controls the gain of the analog AGC preceding the ADC. This bit only functions when ADAGC = 1. The
gain steps are linear in magnitude. Table 6 shows the AGC's effect on the input full-scale conversion range.
Table 6. Analog AGC Code and Gain Values
AGC GAIN CODE 0000 (default) 0001 0010 0011 0100 0101 0110 0111 TYPICAL FULL-SCALE CONVERSION RANGE (mV) 752 683 626 578 535 500 469 441 AGC GAIN CODE 1000 1001 1010 1011 1100 1101 1110 1111 TYPICAL FULL-SCALE CONVERSION RANGE (mV) 417 394 375 357 341 326 313 300
Color Kill Register
REG 0x0B B7 BW B6 CRKDIS B5 1 B4 0 B3 B2 CTHRSH B1 B0
Black and White (BW) 1 = Chrominance demodulator is disabled and component video output is black and white only. 0 = Chrominance demodulator is enabled (default).
Color Kill Disable (CRKDIS) 1 = Color kill is disabled. 0 = Automatic color kill is enabled (default).
Black and white (BW) control bit takes precedence over CRKDIS.
Color Kill Threshold (CTHRSH) The color kill threshold is relative to the peak-to-peak amplitude of the color burst of the composite video signal at the video inputs (VIN1/VIN2). The threshold values assume the sync amplitude is the standard level.
CTHRSH 0000 0001 0010 0011 (default) 0100 0101 0110 0111 BURST AMPLITUDE (mV) Off Off 19 25 27 29 30 31 CTHRSH 1000 1001 1010 1011 1100 1101 1110 1111 BURST AMPLITUDE (mV) 35 39 40 41 43 45 48 51
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Low-Power, High-Performance NTSC/PAL Video Decoder
Color Test Signal Register
REG 0x0C B7 RAWADC B6 0 B5 TGEnab B4 TGTIM B3 TGSRC B2 0 B1 CBAR B0
MAX9526
ADC-Only Mode (RAWADC) 1 = D9-D0 are the ADC outputs directly without being processed by video demodulator.
0 = D9-D0 are 10-bit YCbCr component video (default). With RAWADC = 1, the D9-D0 output data rate is 54Msps and the LLC clock output is 54MHz. Figure 16 shows the typical setup and hold timings of the output signals with RAWADC = 1. LLC can optionally be inverted by setting LLC_INV = 1 in register 0x0D, B5. With RAWADC = 1 the ADC outputs are filtered with the digital lowpass filter before being routed to D9-D0. The ADC outputs can be directly connected to D9-D0 without filtering by setting RAWADC = 1 and DISAAFLT = 1 in register 0x0F, B5.
D9-D0 ~8ns LLC (54MHz) ~18.5ns ~8ns
Figure 16. Typical Setup and Hold Timings in RAWADC Mode
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Table 7. Output Test Signal Setup
DESCRIPTION STDSEL REGISTER 0x04 B7-5 AUTOD REGISTER 0x04 B4 TGENAB REGISTER 0x0C B5 TGTIM REGISTER 0x0C B4 TGSRC REGISTER 0x0C B3 OUTPUT OF DECODER NO VIDEO INPUT Test pattern VALID VIDEO INPUT Decoded input
Default mode, test pattern has last timing standard used at output Force test pattern with last timing standard used at output Force test pattern with 50Hz timing Force test pattern with 60Hz timing Force 50Hz timing for decoding and test pattern Force 60Hz timing for decoding and test pattern
0X0
1
0
X
X
0X0
1
1
X
1
Test pattern 50Hz test pattern 60Hz test pattern 50Hz test pattern 60Hz test pattern
Test pattern
XXX XXX X0X X1X
X X 0 0
1 1 0 0
0 1 X X
0 0 X X
50Hz test pattern 60Hz test pattern Decoded input with 50Hz timing Decoded input with 60Hz timing
Test Pattern Generation
In default mode, the MAX9526 outputs a test pattern when video is removed. The timing standard for the test pattern is the last timing standard that is at the output of the decoder. If the MAX9526 is reset and has no video inputs, the default output timing standard is 525 lines (60Hz). See register 0x04 for manually configuring the video standard decoding. Table 7 gives some common examples of setting up video standards and test pattern generation.
Test Signal Output Timing Standard (TGTIM) 1 = 525 line, 60Hz frame rate. 0 = 625 line, 50Hz frame rate (default).
This bit is ignored if TGSRC = 1.
Test Signal Timing Source (TGSRC) 1 = Test generator uses timing from incoming video signal (if signal is valid). 0 = Test generator uses internally generated timing (default). Color Bar Select (CBAR)
00 = Black screen (default) 01 = Blue screen 10 = 75% color bars 11 = 100% color bars
Test Pattern Enable (TGEnab) 1 = Force a test pattern at video output. 0 = Output a test pattern if no video is present at the video inputs (default).
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Low-Power, High-Performance NTSC/PAL Video Decoder
Clock and Output Control Register
REG 0x0D B7 0 B6 CLIP B5 LLC_INV B4 SEL_54MHZ B3 XTAL_DIS B2 HSVS B1 DATAZ B0 LLCZ
MAX9526
ITU-R BT.656 Standard Clipping Level (CLIP) 1 = Clip ITU output to Y range is between 64-940 and CbCr range is between 64-960.
0 = Clip ITU output to Y range and CbCr range is between 5-1019 (default).
active video (SAV) code (falls after completing 3FFh 000h of SAV code). Figure 17 shows the horizontal and vertical sync timing. The vertical sync pulse (VS) line transitions are detailed in Table 8. Note that the VS line transitions on pin D0 are shifted by 1 to 2 lines relative to the V flag transitions embedded in the ITU data stream. The V flag transitions embedded in the ITU data stream follow the ITU-R BT.656-4 standard.
Inverted Line-Locked Clock (LLC_INV) This signal inverts the polarity of the line-locked clock that is output from the MAX9526. This can be used to solve board level timing problems for other devices. 1 = Invert LLC clock. 0 = Do not invert LLC clock (default). Input Clock Frequency Select (SEL_54MHz) 1 = 54MHz clock at XTAL/OSC input. 0 = 27MHz clock at XTAL/OSC input (default).
This bit is only applicable when the crystal oscillator is disabled (XTAL_DIS = 1).
Data Output Disable (DATAZ) 1 = Logic data outputs (D9-D0) are disabled and placed in high-impedance state. 0 = Logic data outputs (D9-D0) are enabled (default).
The DATAZ bit forces data outputs high impedance regardless of whether the device is in shutdown.
Crystal Oscillator Disable (XTAL_DIS) 1 = XTAL/OSC is either a 27MHz or a 54MHz CMOS clock input. 0 = Enables the 27MHz crystal oscillator (default). Horizontal/Vertical Sync Output (HSVS) 1 = D1 and D0 output horizontal and vertical sync pulses, respectively. 0 = D1 and D0 are LSBs of digital component video output (default). The rising edge of horizontal sync (HS) coincides with the end of active video (rises after 3FFh 000h of EAV code). The falling edge coincides with the start of
Clock Output Disable (LLCZ) 1 = Logic clock output (LLC) are disabled and placed in a high-impedance state. 0 = Logic clock output (LLC) is enabled (default).
The LLCZ bit forces LLC high impedance regardless of whether the device is in shutdown.
Table 8. VS (Pin D0) Line Transitions
VERTICAL SYNC PULSES (VS on Pin D0) Field 1 Field 2 Start (VS = 1) Finish (VS = 0) Start (VS = 1) Finish (VS = 0) 625 Line 623 Line 21 Line 309 Line 335 525 Line 2 Line 21 Line 265 Line 284
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
LLC
D9-D2 CB359 Y718 CR359 Y719 BLANK BLANK BLANK BLANK BLANK BLANK CB0 Y0 EAV(XY) EAV(FF) EAV(00) EAV(00) SAV(FF) SAV(00) SAV(00) SAV(xy) CR0
HS
VS = 1 VS = 0
2 CLK
1 CLK
2 CLK
Figure 17. Horizontal and Vertical Sync Timing
PLL Control Register
REG 0x0E B7 0 B6 0 B5 LLC_MODE B4 B3 PLLBYP B2 B1 PLLBW B0
Line-Locked Clock Mode (LLC_MODE) 0X = Async mode or line-locked mode is set automatically (default). 10 = PLL is forced to line-locked mode.
11 = PLL is forced to async mode.
Line-Locked PLL Tracking Speed (PLLBW) PLLBW controls a digital loop filter that sets the bandwidth of the line-locked PLL. 000 = 180Hz
001 = 250Hz 010 = 375Hz 011 = 500Hz (default) 100 = 750Hz 101 = 1kHz 110 = 1.5kHz 111 = 2kHz
PLL Bypass Mode (PLLBYP) When PLLBYP = 1, the ADC and the decoder use the input crystal or clock (XTAL/OSC, XTAL2) directly. 1 = Bypass the PLL.
0 = PLL is enabled (default).
Miscellaneous Register
REG 0x0F B7 0 B6 0 B5 DISAAFLT B4 1 B3 B2 SSLICE B1 B0
Disable Digital Anti-Aliasing Filter (DISAAFLT) Disable the digital anti-aliasing filter following the ADC. 1 = Disables filter.
0 = Enables filter (default).
Sync Slicing Level (SSLICE) Sets the sync slicing level. 1111 = Slice at 240 (decimal), near the blanking level.
1000 = Slice at 128 (decimal), near the center of the sync (default). 0100 = Slice at 64 (decimal), about 25% of the sync. 0000 = Slice at 0 (decimal), near the bottom of the sync. All values between 0000 and 1111 are valid.
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Low-Power, High-Performance NTSC/PAL Video Decoder
Pin Configurations
MAX9526
TOP VIEW
DVDDIO DGND DVDD N.C. N.C.
TOP VIEW
LLC VIN1 1 VREF 2 VIN2 3 D7 26 D8 27 D9 28 N.C. 29 VIN1 30 VREF 31 VIN2 32 16 D3 15 D2 14 D1 AGND 4 AVDD 5 XTAL2 6 XTAL/OSC 7 I.C. 8 DEVADR 9 DVDD 10 DGND 11 SDA 12 SCL 13 IRQ 14
+
28 D9 27 D8 26 D7
D6
D5
25 24 23 22 21 20 19 18 17
D4
MAX9526
25 D6 24 DVDDIO 23 DGND 22 DVDD 21 LLC 20 D5 19 D4 18 D3 17 D2 16 D1 15 D0
MAX9526
13 D0 12 IRQ 11 SCL
+
1 AGND 2 AVDD 3 XTAL2 4 XTAL/OSC 5 I.C. 6 DEVADR 7 DVDD 8 DGND
*EP 9 N.C.
10 SDA
TQFN
*EP = EXPOSED PAD
QSOP
Chip Information
PROCESS: CMOS
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Typical Operating Circuit
+3.3V OR +1.8V 0.1F +1.8V 0.1F 0.1F 0.1F
CVBS INPUT 1
37.5
0.1F
AVDD VIN1
DVDD
DVDDIO LLC D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVDDIO 10k CLK 27MHz D9 D8 D7 D6 D5 PARALLEL OUTPUT D4 D3 D2 D1 D0
37.5 0.1F
VREF
CVBS INPUT 2
37.5
0.1F VIN2
MAX9526
37.5
DVDDIO
IRQ 47pF
IRQ
10k SDA SCL ADDR
10k SDA SCL DEVADR I2C INTERFACE I.C. AGND
XTAL/OSC 27MHz XTAL2 DGND 47pF GND
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Low-Power, High-Performance NTSC/PAL Video Decoder
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE 28 QSOP 32 TQFN-EP PACKAGE CODE E28-1 T3256-1 DOCUMENT NO. 21-0055 21-0183
MAX9526
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QSOP.EPS
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
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Low-Power, High-Performance NTSC/PAL Video Decoder
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
MAX9526
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Low-Power, High-Performance NTSC/PAL Video Decoder MAX9526
Revision History
REVISION NUMBER 0 1 2 REVISION DATE 5/09 7/09 2/10 Initial release Corrected TQFN package diagram Added automotive parts DESCRIPTION PAGES CHANGED -- 36, 37 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
38 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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